QWE AI Academy A solo engineer just taped out what looks like the first fully open source Ethernet switch ASIC – a 3-port, 100 Mbps cut-through switch on GlobalFoundries 180 nm – and the project blew up on Hacker News over the past week. If you’ve ever wondered what actually goes into designing an Ethernet switch ASIC, this is the moment to look, because the entire design, floorplan, and constraint list are public.
Here’s the key takeaway upfront: designing a switch ASIC is 90% architecture decisions made before you write Verilog, and the biggest one – cut-through vs store-and-forward – is still contested in 2026. We’ll walk through the decision using this trending project as the reference.
The trending project, in one paragraph
The design is an unmanaged cut-through 3-port 100 Mbps switch fabbed on Global Foundries 180 nm, built by an independent engineer and taped out on the Tiny Tapeout gf26b shuttle chip, part of the second wafer.space run. The floorplan occupies 711.2 x 325 μm of area – smaller than a grain of salt. Silicon bring-up is expected to start 2026-11-15. The author’s motivation, in their own framing: recent FCC decisions have put the central importance of networking equipment top of mind, and in doing so, have also put the total absence of any entirely open source networking equipment hardware at the top of my mind. That’s the itch this scratches.
You can read the full write-up at the author’s Tales on the wire blog. The Hacker News discussion thread is worth reading for the reactions from people who design switch silicon for a living.
What a switch ASIC actually is
Strip away the marketing and a switch ASIC is three things glued together: PHYs (the analog front-end that talks to copper or fiber), MACs (the digital block that turns bits into Ethernet frames), and a switch fabric with buffers and a forwarding engine that decides which egress port each frame should leave on.
Every design choice in the ASIC – port count, buffer size, latency, power – falls out of how you build those three blocks and how they connect. The trending open source design is small enough that it fits in a single Tiny Tapeout tile, which forced the author into some brutal simplifications. That’s actually why it’s a good teaching example: the constraints are visible.
Method A vs Method B: cut-through vs store-and-forward
This is the fork in the road every switch ASIC designer hits on day one. The choice affects latency, buffer sizing, error behavior, and whether your chip is even legal to call a switch in some engineers’ eyes.
| Property | Cut-through | Store-and-forward |
|---|---|---|
| Forwarding starts | After header (~6 bytes) | After full frame received |
| Typical latency | 5-10 μs | 20-60 μs |
| FCS validated before forward? | No | Yes |
| Buffer requirement | Small | At least one full frame per port |
| Handles port-speed mismatch? | No (falls back) | Yes |
Those latency numbers are based on measurements from switch platforms like Cisco Catalyst 9000 or Arista 7280R series – not vendor marketing. Cut-through designs typically deliver lower latency, but there are tradeoffs. The biggest issue is that cut-through switches will forward corrupted frames, since they don’t wait to see if the checksum at the end of each frame is valid. A router or other store-and-forward device will keep them from leaving the data center, which is why most enterprise gear still ships in store-and-forward by default.
The trending project picked cut-through. Why? Buffer memory on 180 nm is expensive in area, and a single-tile Tiny Tapeout project has almost no room. Cut-through lets you get away with a shift register instead of a full frame buffer.
Walkthrough: how the winning design was actually built
Here’s the sequence of decisions the author made, in the order they had to make them. If you’re building your own switch ASIC – even in an FPGA – this is the same order you’ll face.
- Pick a fab and shuttle. Full-mask 180 nm tapeout runs around $500K, driven primarily by mask sets and NRE – not wafer costs. A Tiny Tapeout tile on the same node is closer to $50-$300. That price gap is the entire reason this project exists.
- Budget your pins first, not your gates.Since I will be taping this first generation chip out over the Tiny Tapeout shuttle chip, using purely digital tiles, I’m constrained by the limits of these pins. Three MII-style ports is what fits. Ten ports doesn’t, no matter how clever your RTL is.
- Choose the forwarding mode. Cut-through, for the buffer-area reason above.
- Design the MAC. IEEE 802.3 compliance for framing, preamble detection, and FCS calculation – you can skip nothing here or the switch won’t interop with real hardware.
- Design the fabric. With three ports and cut-through, a tiny crossbar with a MAC-address lookup table is enough. No arbitration, no VOQs, no fancy scheduling.
- Verify in simulation, then in FPGA, then on silicon. The FPGA prototype is what proved the design actually forwarded real Ethernet frames before committing to a tapeout slot.
Pro tip: If you’re prototyping a switch on an FPGA before ASIC, drop your design between two real Linux hosts and let the kernel route traffic through it. As the author discovered, Linux’s network management favors wired connections over wireless when available. So as soon as the switch became available all my ethernet traffic had stopped going over my wireless interface (wlp3s0) and was instead routed through my wired interface (enp2s0). Free integration test.
Edge cases the tutorials skip
These are the gotchas you won’t find in the standard “switch ASIC 101” article, and they matter more than any of the textbook material above.
Cut-through silently becomes store-and-forward under port-speed mismatch
Per NVIDIA’s own switch documentation, an interface of 10GbE passing traffic to 40GbE interface causes the switch to store the whole packet before sending it, which increases latency. Your carefully-designed 5 μs cut-through chip will behave like a store-and-forward chip the moment someone plugs a slower link into a faster one. Plan for it in the architecture, not in errata.
The FCS-forwarding debate is not settled
One commenter on the trending HN thread summed it up: “I had a Google interview collapse because the last interviewer was a Principle Engineer who just couldn’t accept that a switch will ever forward a frame before reading in full and checking the FCS.” Real engineers still argue about whether cut-through is acceptable at all. If you’re building for a market where corrupted-frame propagation is unacceptable (finance backends, medical devices), store-and-forward is the safer default even at 6x the latency.
The open silicon supply chain is fragile
Efabless – the platform Tiny Tapeout originally ran on – announced it was shutting down operations due to funding challenges in March 2025. Tiny Tapeout has since migrated to wafer.space shuttles (that’s the “WS-2606” run this project sits on, per the Tiny Tapeout chips page). Any tutorial from 2023-2024 that tells you to “submit to chipIgnite” is now sending you to a dead end.
What to do next
Don’t start with a switch. Start with something smaller on the same toolchain. Go to tinytapeout.com, work through the digital-design lessons, submit a blinker for the next open shuttle (TTSKY26c closes September 7, 2026 as of writing – check the site for current dates). Once you’ve held your own silicon in your hand, then read the essenceia write-up again with fresh eyes. The switch ASIC architecture will make ten times more sense once you understand the tile constraints from the inside.
FAQ
Do I need a PhD in VLSI to design a switch ASIC?
No. The trending project was built by one person on a hobbyist budget using open source tools and a $150-ish shuttle slot. Domain knowledge of Ethernet framing helps more than a semiconductor degree does.
Why 180 nm in 2026? Isn’t that ancient?
Because the mask set on a leading-edge node costs millions and takes a year. 180 nm gets you real silicon, in your hand, for the price of a used laptop. For a 100 Mbps switch you don’t need transistors any smaller – Ethernet at 100 Mbps ran on 180 nm just fine in 2001, and physics hasn’t changed. The moment you want 10 GbE or beyond, though, the SerDes requirements push you to 28 nm or below, and the economics flip completely – that’s why merchant switch silicon at Broadcom-class throughput is a company-scale endeavor, not a hobbyist one.
What’s the practical difference between designing this as an ASIC vs an FPGA?
An FPGA is where you should start – same RTL, no tapeout cost, iteration in minutes. ASIC gives you lower power per port, lower unit cost at volume, and better latency because you can hand-tune the critical path. For a 3-port 100 Mbps switch the FPGA is arguably the better answer forever. The ASIC only wins the moment you’re shipping thousands of units or need something an FPGA physically can’t do.